1. Field of the Invention
The present invention relates to a power semiconductor device, and particularly to an insulated gate semiconductor device favorably used as a power switching element.
2. Description of the Related Art
In recent years, power supply devices used in the power electronics field are strongly required to be more compact with higher performance. In accordance with this demand, power semiconductor devices have been improved to operate with lower loss and less noise, as well as higher breakdown voltage and larger electric current. Under the circumstances, an improved device (which is referred to as an IEGT (Injection Enhanced Gate Transistor) hereinafter) obtained by improving an IGBT (Insulated Gate Bipolar Transistor) is attracting attention as a device that can reduce the turn-off loss, as well as reducing the ON-state voltage.
As a typical structure of an IEGT, a structure is known in that a dummy cell is disposed between the main cells to reduce the area ratio of the main cells (see, for example, U.S. Pat. No. 5,585,651, and U.S. Pat. No. 6,445,048). According to this structure, since the main cell area is reduced, a restriction is imposed on holes to be injected from the collector side into the n-base layer, and then exhausted to the emitter side through the main cell, in the ON-state of the IEGT. This brings about an increase in injection efficiency of electrons to be injected from the emitter side into the n-base layer. As a consequence, the conductivity modulation of the n-base layer is promoted to achieve a low ON-voltage.
FIG. 20 is a plan view showing the layout of a conventional IEGT chip having dummy cells. FIG. 21 is a sectional view taken along a line XXI—XXI in FIG. 20, which corresponds to the periphery of the IEGT chip shown in FIG. 20. As shown in FIGS. 20 and 21, this device has an active region R11 disposed on the central side of a semiconductor substrate (active layer) Sub, and a junction termination region R12 disposed on the periphery of the substrate Sub and surrounding the active region R11. The semiconductor substrate Sub is formed of an n-layer having a high resistivity, and is used as an n-base layer 101.
As shown in FIG. 21, a p-collector layer 103 having a high impurity concentration is disposed on the bottom side of the semiconductor substrate Sub. On the other hand, on the top side of the semiconductor substrate Sub, a plurality of trenches 104 are formed at intervals in the active region R11, such that main cells MR and dummy cells DR are alternately partitioned. In each of the main cells MR, a p-base layer 107 is disposed on the n-base layer 101. N-emitter layers 108 are formed in the surface of the p-base layer 107. In each of the dummy cells DR, a p-buffer layer 109 is disposed on the n-base layer 101. Furthermore, a p-surrounding buffer layer 109a is disposed to surround the main cells MR and dummy cells DR.
A collector electrode 111 is disposed on and in contact with the p-collector layer 103. An emitter electrode 112 is disposed on and in contact with the p-base layer 107 and n-emitter layers 108. An insulating layer 102 is disposed between the emitter electrode 112 and the p-buffer layer 109 in the dummy cells DR. A gate electrode 106 is buried in each of the trenches 104, while it is wrapped in a gate insulating film 105. The gate electrode 106 faces, through the gate insulating film 105, that portion of the p-base layer 107, which is sandwiched between the n-base layer 101 and n-emitter layer 108.
A p-guard ring layer 113 having a high impurity concentration is disposed in the boundary portion between the active region R11 and junction termination region R12, and is electrically connected to the emitter electrode 112. An n-outer ring layer 114 having a high impurity concentration is disposed along the chip edge in the junction termination region R12, and is electrically connected to the collector electrode 111. A plurality of p-field limiting ring layers 116 having a high impurity concentration are disposed between the p-guard ring layer 113 and n-outer ring layer 114. The combination of these layers 113, 114, and 116 contributes to a high breakdown voltage on the top side of the substrate Sub. A stopper electrode 115 and floating electrodes 117 are disposed on and in contact with the n-outer ring layer 114 and p-field limiting ring layers 116, respectively.
In this IEGT, each of the main cells MR forms a narrow current passage connecting the n-base layer 101 to the emitter electrode 112. This arrangement provides an increase in resistance in the ON-state of the IEGT against the flow of holes from the n-base layer 101 into the emitter electrode 112 through the p-base layer 107 in the main cell MR, thereby restricting the holes being exhausted into the emitter electrode 112. As a consequence, the injection efficiency of electrons from the n-emitter layers 108 into the n-base layer 101 improves, thereby promoting conductivity modulation of the n-base layer 101, resulting in a low ON-voltage.
As described later, according to research conducted by the present inventors, it has been found that conventional IEGTs have insufficient points to lower the ON-voltage. In light of the problems of the conventional technique, there are demands for a power semiconductor device that has a high current-carrying ability in the ON-state to make the ON-voltage lowered.